ID=DFLL48, GEN=GCLK0
Generic Clock Control
| ID | Generic Clock Selection ID 0 (DFLL48): DFLL48 1 (FDPLL): FDPLL 2 (FDPLL32K): FDPLL32K 3 (WDT): WDT 4 (RTC): RTC 5 (EIC): EIC 7 (EVSYS_0): EVSYS_0 8 (EVSYS_1): EVSYS_1 9 (EVSYS_2): EVSYS_2 10 (EVSYS_3): EVSYS_3 11 (EVSYS_4): EVSYS_4 12 (EVSYS_5): EVSYS_5 13 (EVSYS_6): EVSYS_6 14 (EVSYS_7): EVSYS_7 15 (EVSYS_8): EVSYS_8 16 (EVSYS_9): EVSYS_9 17 (EVSYS_10): EVSYS_10 18 (EVSYS_11): EVSYS_11 19 (SERCOMX_SLOW): SERCOMX_SLOW 20 (SERCOM0_CORE): SERCOM0_CORE 21 (SERCOM1_CORE): SERCOM1_CORE 22 (SERCOM2_CORE): SERCOM2_CORE 23 (SERCOM3_CORE): SERCOM3_CORE 24 (SERCOM4_CORE): SERCOM4_CORE 25 (SERCOM5_CORE): SERCOM5_CORE 26 (TCC0_TCC1): TCC0_TCC1 27 (TCC2_TC3): TCC2_TC3 28 (TC4_TC5): TC4_TC5 29 (TC6_TC7): TC6_TC7 30 (ADC): ADC 31 (AC_DIG): AC_DIG 32 (AC_ANA): AC_ANA 33 (DAC): DAC 35 (I2S_0): I2S_0 36 (I2S_1): I2S_1 |
| GEN | Generic Clock Generator 0 (GCLK0): Generic clock generator 0 1 (GCLK1): Generic clock generator 1 2 (GCLK2): Generic clock generator 2 3 (GCLK3): Generic clock generator 3 4 (GCLK4): Generic clock generator 4 5 (GCLK5): Generic clock generator 5 6 (GCLK6): Generic clock generator 6 7 (GCLK7): Generic clock generator 7 8 (GCLK8): Generic clock generator 8 |
| CLKEN | Clock Enable |
| WRTLOCK | Write Lock |